Field of the Invention
The invention relates to a Not AND (NAND) type flash memory and such semiconductor memory device, and relates particularly to a data scrambling method of a NAND type flash memory.
Description of Related Art
A NAND type flash storage has a memory array which includes a plurality of blocks, wherein a NAND string constructed by a plurality of storage cells connected in series is formed in one block. Typically, a read-out or programming of data is performed with one page as the unit, and erasing of data is performed with one block as the unit.
Patent document one discloses a data writing method by which reliability of operation for a NAND type flash memory may be improved. The writing method is: selecting a scrambling method based on the address of a word line, scrambling the data to be written according to the selected scrambling method, and writing the scrambled data to the corresponding page.
The storage cells of the NAND type flash memory includes an N-type metal oxide semiconductor (MOS) structure, wherein the N-type MOS structure has a floating gate (charge accumulation layer) and a control gate. When electrons accumulate at the floating gate, the threshold value of the storage cell shifts to the positive direction, wherein this state is data “0”. On the other hand, when electrons are discharged from the floating gate, the threshold value shifts to the negative direction, wherein this state is data “1”. When the blocks are erased in a batch, all of the memory cells in the blocks are data “1”.
In this kind of flash memory, when programming (write-in) or erasing is repeated, the reliability of the stored data deteriorates. For example, a situation where a ratio of data “0” is overwhelmingly more than data “1” or the opposite situation when a ratio of data “1” is overwhelmingly more than data “0” when programming is performed. Due to miniaturization and high integration of memory cells and the distance between memory cells becoming shorter, adjacent memory cells may be in a capacitive coupling situation and interfere with each other. When the storage cells around the periphery of one storage cell are all data “0”, then the memory cell at the center is influenced by the memory cells of the periphery and has a higher threshold value than compared to a case when they are all data “1”. Furthermore, the uneven distribution of data “0” or data “1” may have an adverse effect on the characteristics of the sense amplifier when data is read-out due to a difference in the floating voltage of the source line voltage.
Therefore, from a reliability perspective, an ideal ratio of data “0” to data “1” is approximately 0.5. One method for implementing this ratio is a data scrambling scheme. Namely, random numbers are used to scramble the data to be programmed, and then the scrambled data is programmed to the memory array. Regarding scrambling, for example, the programming addresses may be used as seeds such that the random number may be changed for every address. In this way, data “0” and data “1” may be disposed randomly in the column direction and the row direction of the memory array. In addition, during read-out operation, the scrambled data is converted to the original data by using the random number that was used in scrambling to descramble the data that is read-out by the memory array.
In the NAND type flash memory, the memory cell after data is erased is data “1”, and the read-out operation after erasing, for example, is required to output data “FFh”. Therefore, under the condition when data scrambling is used in the NAND type flash memory, descrambling needs to be restricted such that the data after erasing are all “1”. On the other hand, there are times where the data that is programmed by data scrambling are all “1”, even though the probability is very small. Under the situation where this type of data is read-out, descrambling is required to be performed. Due to this type of limitation, a flag bit is provided in a redundant region of the NAND type flash memory for determining whether the page is in an erased state or in a programmed state. The flag bit is data “1” when a block including the page is erased, and is changed to data “0” when the page is programmed.
FIG. 1A is a flow of a programming operation and FIG. 1B is a flow of a read-out operation. First, in a programming operation, a programming command is received from an external controller (S10). Then, the address and the data to be programmed are received (S12). Scrambling is performed on the data received (S14). Furthermore, the flag of data “1” is changed to “0”, so as to show the selected page has already been programmed (S16). Next, the scrambled data and the flag are programmed to the selected page (S18).
In the read-out operation, when a read-out command and address are inputted from the external controller (S20), data is read-out from the selected page of the memory array (S22). Next, determination of the flag is performed (S24). If the flag is “0”, the data that is read-out is descrambled (S26), and converted to the original data and outputted (S28) even if all the data are “1” since that data is programmed data. On the other hand, if the flag is “1”, then the data that is read-out is data after erasing, therefore descrambling is not performed and the data is outputted directly (S28).
Here, in the NAND type flash memory, a function (referred to as partial page programming for convenience below) for programming data on a same page n number of times consecutively may be executed (n is a natural number greater than or equal to 2). When high integration further advances, the size of one page increases and there are situations where the amount of data being programmed is less than the size of one page. If data can be programmed only once on the same page, the usage efficiency of each page decreases. Conversly, if a plurality of data is programmable on one page, those data must be programmed on a plurality of pages, then the time required for the program increases significantly. On the other hand, programming data on the same page n number of times consecutively means that a high programming voltage that will be applied to the page n number of times, so the number of times of programming is limited. For example, if n=4, then data can be programmed to the same page 4 times consecutively. Hereinafter, the data programmed to the same page by partial page programming is referred to as partial data.
In partial page programming, for example, a program command is received from the external controller; then the column address Ax and the row address Ay1 are received; then a partial data D1 is received; then when a finish command is received, programming of the partial data is started. That is to say, the partial data D1 is programmed to the page selected by the column address Ax starting from the row address Ay1. During this period, the NAND flash memory outputs a busy signal to the external controller such that access is restricted. At the point when access restriction is lifted, the ready signal is outputted to the external controller. When the external controller receives the ready signal, in order to program the next partial data, similar to the above, a program command, a row address Ay2, a partial data D2 and a finish command are sent to the NAND flash memory, and the NAND flash memory programs a partial data D2 to the same selected page starting at the row address Ay2. This type of process is repeated n number of times and as a result, n number of partial data D1, D2, . . . , Dn are programmed on one page.
In the NAND type flash memory which may execute this type of partial page programming, in the case when the data scrambling scheme is adopted, it must be determined whether the partial data in the page was programmed or was deleted. Since the size of the partial data programmed by partial page programming is not fixed but variable, data scrambling can not be properly executed without determining the boundaries of the partial data.